Some nonvolatile semiconductor memories use the mechanisms of Fowler-Nordheim (F-N) tunneling and hot-electron injection to store data. Practically, in order to erase/program data using the F-N tunneling and hot-electron injection effects, high voltages of 15V through 20V may be needed together with a power source voltage. In general, a semiconductor memory device operable under a low power source voltage can employ a high-voltage generation circuit to generate a power source voltage and a high voltage.
FIG. 1 shows a high-voltage generation circuit of a semiconductor memory device according to the conventional art. The high-voltage generation circuit shown in FIG. 1 includes a high-voltage generator 10, a power-voltage driver 20, and a ground-voltage driver 40. The high-voltage generation circuit drives an output signal VOUT to a high voltage that is greater than a power source voltage VDD in response to a high-voltage control signal HVCON. The power-voltage driver 20 drives the output signal VOUT to the power source voltage VDD in response to a ground-voltage control signal GNCON.
As shown in FIG. 1, the power-voltage driver 20 includes depletion NMOS and PMOS transistors, 21 and 23, connected between an output node N60 and the power source voltage VDD. The NMOS transistor 21 is gated by the power-voltage control signal VDCON while the PMOS transistor 23 is gated by an inverse signal nVDCON of the power-voltage control signal VDCON.
However, in the conventional high-voltage generation circuit, charges accumulated at the output node N60 may leak toward the power source voltage VDD when the output signal VOUT is driven to a high voltage. In more detail, when the output signal VOUT is being driven to a high voltage, the power-voltage control signal VDCON goes to a logical “L” level (i.e., the level of the ground voltage VSS) and the inverse power-voltage control signal nVDCON goes to a logical “H” level (i.e., the level of the power source voltage VDD). In response, a voltage level at a common junction N22 shared by the two depletion NMOS transistors 21 and 25 is set to the level of VDD+Vt, while a voltage level at a common junction N24 shared by the NMOS and PMOS transistors 21 and 23 is set to the level of Vt. Here, Vt denotes a threshold voltage of the depletion NMOS transistor 21 or 25.
When the power source voltage VDD is pulled down to a lower voltage, the PMOS transistor 23 may turn on in response to the reduced VDD. As a result, when the output signal VDOUT is being driven to a high voltage, the high voltage generation efficiency may be degraded because charges accumulated at the output node N60 may leak into the power-voltage driver 20.